1. Field of the Invention
The present invention relates to the integrated circuit memory, and particularly relates to a green MOSFET transistor serving as the select transistor for a resistive random access memories and methods of operating the same.
2. Description of Prior Art
Recently, a new type of memory, the resistive random access memory (RRAM) has attracted much attention due to its high memory density, low-cost, lower power consumption and high endurance. The bi-stable resistance states of the RRAM memory cell can be changed electrically when applied to a large voltage or current pulse; and the RRAM memory cell can maintain the resistance state for a long period of time after the voltage or current pulse.
An RRAM includes an array of memory cells organized in rows and columns. FIG. 1 is a schematic diagram of a conventional RRAM array. As shown in FIG. 1, a memory cell 100, which includes a switching resistor 101 and a select transistor 102, is referred to as “1T1R” cell. The select transistor 102 is typically a MOSFET transistor for accessing the switching resistor 101 to perform the read/write operations. We assume the select transistor is n-type MOSFET for convenience in this text. The switching resistor 101 has two terminals, one is connected to a bit-line 103, and the other is connected to the drain of the select transistor 102. The gate of the select transistor 102 is connected to a word-line 104, and the source of the select transistor 102 is grounded. The bistable resistance states of the switching resistor 101 represent the digital data ‘0’ and ‘1’. The resistance states are switchable by applying a large enough voltage or current pulse through the switching resistor 101. For convenience, a high resistance state is arbitrarily defined as data ‘1’, a low resistance state as data ‘0’.
FIG. 2 illustrates the waveforms for a conventional method of operating the RRAM in FIG. 1. The pulse height and duration shown in FIG. 2 are only for illustration purposes (and similarly for FIGS. 7, 12, 16, and 19), and the preferred range of pulse height and duration will be mentioned in following embodiments accordingly. The method includes a write operation and a read operation.
During the write operation, a voltage pulse VH (typically height ˜Vcc) is applied to the bit-line 103, where Vcc is the voltage source from external power supply, typically available with 3.3 v, 2.5 v, or 1.8 v depending on the system specifications. The voltage pulse is applied on the gate through the word-line 104 to turn on the select transistor 102. A large enough current pulse through the switching resistor 101 is resulted. Depending on the magnitude and duration of the current pulse for enough heat dissipation in the resistor, the resistance state can be changed from high to low resistance state (referred to as SET operation) as “0”, or reversely, from low to high resistance state (referred to as RESET operation) as “1”.
During the read operation, a voltage pulse with pulse height VL (typically 0.1 v to 1 v) is applied to the bit-line 103. Then the select transistor 102 is turned on by applying a voltage pulse on the gate through the word-line 104. The voltage pulse height and duration is selected properly so that the current flowing through the resistor is small enough to avoid read disturb (by the small heat dissipation) and also large enough for sense amplifier to determine the resistance. The sense amplifier compares the current through the switching resistor 101 with respect to a reference current from periphery circuit (not shown in FIG. 1). For convenience, data “0” is represented by a larger current with respect to the reference current (corresponding to low resistance state), and data “1” by a smaller read current (corresponding to high resistance state).
The leakage current of the select transistor is undesirable as it degrades the retention of the switching resistors 101 (due to the continuous dissipation of a small amount of heat in the resistor by the leakage current). It is also difficult to scale down the operating voltage and the size of the MOSFET select transistor due to a need of large current pulse during write.
One solution to this problem is to adopt the new green MOSFET transistor (gFET) as the select transistor, which has been proposed by C. Hu et. al. in the paper titled ‘Green Transistor-A VDD Scaling Path for Future Low Power ICs’. The gFET can enhance the GIDL current based on band-to-band tunneling (BTBT) by implanting an opposite type of dopant into the source or drain. The BTBT is a mechanism that carriers tunnel through the energy barrier across the valence band and conduction band.
FIG. 3a is a schematic diagram of a conventional gFET. The conventional gFET comprises: a silicon on insulator (SOI) 310 and a gate stack (not labeled). The silicon on insulator (SOI) 310 includes a substrate 311, a buried oxide 312 and a top silicon 313. The gate stack is formed on the top silicon 313 and includes a gate oxide 316 and a gate 317. A drain 315 and a source 314 with different conductivities are formed respectively on two sides of the gate oxide 316 and in the top silicon 313. A lightly-doped region 319 and a pocket implant region 318 are formed in the top silicon 313 and neighboring to each other. The lightly-doped region 319 and the pocket implant region 318 are respectively aligned with the gate 317 and gate oxide 316. Both of the pocket implant region 318 and the lightly-doped region 319 have the same conductivity as the drain 315. The source 314, the drain 315 and the lightly-doped region 319 are all in contact with the buried oxide 312. The pocket implant region 318 is of less depth and is not directly in contact with the buried oxide 312.
For convenience, the type of the gFET is defined by the type of the pocket implant region 318. For example, a p-type gFET includes a p-type pocket implant region 318, an n-type source 314, and a p-type drain 315. An n-type gFET includes an n-type pocket implant region 318, a p-type source 314, and an n-type drain 315.
As an example, a p-type gFET is described in details below.
FIG. 3b is a band diagram of the band-bending near the pocket implant region 318, wherein valence band electrons may tunnel into the conduction band of the source 314 if the band is bent large enough, e.g. the solid curve 301, 301a denotes the band-bending when the gFET is turned on with the gate 317 negatively biased with respect to the source 314 and the potential of the implant region 318 lowered. Therefore, the upper edge of the valence band (Ev) of the implant region 318 is higher than the lower edge of the conduction band (Ec). Under this condition, the electrons in the valence band can start tunneling into the conduction band, leaving holes in the valence band correspondingly. The dotted curves 302, 302a represent the band-bending when the gFET is turned off with no bias across the gate 317 and the source 314. The upper edge of the valence band (Ev) of the implant region 318 is lower than the lower edge of the conduction band (Ec), which leads to a large barrier between the conduction band and the valence band and no carriers can tunnel through.
FIG. 3c illustrates the currents when a p-type gFET is turned on. Referring to FIG. 3a, the p-type gFET includes a P+-type pocket implant region 318, an N+-type source 314, a P+-type lightly-doped region 319 and a P+-type drain 315. Referring to FIGS. 3b and 3c, when the (n-type) source 314 is biased to a voltage (Vs) higher than a voltage (Vd) applied to the (p-type) drain 315 (Vsd>0), and the gate 317 is biased to a voltage (Vg) more negative enough with respect to the source 314 (for enough band-bending), the valence band electrons in the p-type pocket implant region 318 will tunnel into the n-type source 314 by the BTBT mechanism. The holes in the p-type pocket implant region 318 will move toward the p-type drain 315 through the lightly-doped region 319 by drift mechanism due to electrical field. As a result, a current is flowing from the source 314 to the drain 315, and the p-type gFET is turned on.
The gFET has many advantages over the conventional MOSFET, such as smaller sub-threshold swing, lower threshold voltage, low voltage operation, less power consumption and higher driving current. Thus, the gFET is a great replacement of the conventional MOSFET as select transistor in the memory cell mainly for its low voltage operation.